1. Field of Invention
The present invention relates to a signal control circuit used in a circuit or device for communicating data, address, control signals via bus between a main processing circuit, such as a central processing unit CPU, and a subsidiary processing circuit, such as a memory circuit or an input-output circuit. More particularly, the present invention relates to a signal control circuit for controlling input/output of data, address, control signals to and from the subsidiary processing circuit.
2. Description of Related Art
Various electronic devices, control devices are provided with a device or system for controlling bus signals such as data, address, and control signals. The bus signal controlling device includes a main processing circuit, such as a CPU, and a subsidiary processing circuit, such as a memory circuit, an input/output circuit. In the bus signal controlling device, the main processing circuit is connected to the subsidiary processing circuit via a bus. The bus signal controlling device controls input/output of bus signals between the main processing circuit and the subsidiary processing circuit.
For example, a data storage device is widely used in computers, printers. The data storage device includes a CPU and a memory circuit, such as a random access memory (RAM), a read only memory (ROM). The CPU and the memory circuit are mounted on a single substrate, and are connected with each other via address bus, data bus, and control signal lines. The data storage device serves to perform data processing operation such as data storage processing between the CPU and the memory circuit. Each set of bus signals, used in the above-described device, is a digital signal constructed from a plurality of bits.
In recent years, in order to improve the performance of the computers printers, the operation speeds and data processing abilities of the main processing circuit and the subsidiary processing circuit are greatly enhanced. The operation speed of the CPU is greatly enhanced. The capacity of the memory circuit is greatly increased.
When the operation speeds and the data processing abilities of the main processing circuit and of the subsidiary processing circuit are enhanced, the number of bits constituting each set of bus signals, transferred between the main processing circuit and the subsidiary processing circuit, is also increased. Input/output rate of the bus signals between the main processing circuit and the subsidiary processing circuit is also increased.
When the data processing ability of the CPU is enhanced and the capacity of the memory circuit is increased, for example, the number of bits constituting each set of data and each set of address that are transferred between the CPU and the memory circuit is increased. When the operation speed of the CPU is increased and the reading/writing frequency of the memory circuit is increased, the input/output rate of data and address between the CPU and the memory circuit is increased.
When the number of bits constituting each set of bus signals is increased and the input/output rate of the bus signals is increased, bus signals comprised of a large number of bits are repeatedly and frequently transferred between the main processing circuit and the subsidiary processing circuit. Accordingly, bus signals, having the large number of bits, rapidly change in the bus that connects the main processing circuit and the subsidiary processing circuit.
At an instant when a bus signal having a large number of bits rapidly changes, noise will possibly occur within the bus signal. Especially when all of the bits constituting the bus signal simultaneously rise or fall to the same binary state, noise will highly possibly occur in the bus signal. Immediately after a ten-bit address bus signal changes from xe2x80x9c0000000000bxe2x80x9d to xe2x80x9c1111111111bxe2x80x9d, for example, noise will possibly occur in the address bus signal. As a result, a non-stable address signal, influenced from the noise, is inputted to the main processing circuit or to the subsidiary processing circuit. The main processing circuit or the subsidiary processing circuit will possibly detect the received inaccurate address bus signal.
Especially when the memory circuit is constructed from dynamic RAM (which will be referred to simply as DRAM hereinafter), the above-described problem occurs highly likely. The DRAM is a memory circuit that can perform data reading/writing operation rapidly. Especially when the DRAM is used in a so-called page mode, the data reading/writing operation can be performed more rapidly. When performing the rapid data reading/writing operation onto the DRAM, if all the bits constituting each set of data or each set of address signal change simultaneously, noise will highly possibly occur in the data or the address signal. It is noted that during the page mode, a row address is first outputted to the DRAM. Thereafter, a plurality of column addresses are successively outputted to the DRAM, whereby a corresponding plurality of addresses in the single page can be designated.
In order to restrain the above-described noise, it is conceivable to construct the circuit substrate, on which the main processing circuit, the subsidiary processing circuit, and the bus are mounted, into a multilayered structure, thereby increasing a thickness of a pattern for a zero (0) volt (ground voltage) and increasing a ground strength of the circuit substrate. When the circuit substrate is thus constructed in the multi-layered structure, however, the cost required for producing the entire device increases.
The noise can be restrained also when the input/output rate of the bus signal between the main processing circuit and the subsidiary processing circuit is decreased. However, this leads to drop in the entire processing speed of the main processing circuit and the subsidiary processing circuit.
In view of the above-described drawbacks, the present invention is attained to provide an improved signal control circuit that enables input/output of bus signals in accuracy and at a high speed through preventing the bus signals from being inaccurately detected even when noise occurs in the bus signals due to simultaneous changes of the bits located therein.
In order to attain the above and other objects, the present invention provides a signal control circuit for outputting, to a subsidiary processing circuit, control signals for controlling input and output of bus signals with respect to the subsidiary processing circuit, the bus signals being transferred or inputted/outputted via a bus between the subsidiary processing circuit and a main processing circuit, the signal control circuit comprising: a comparing portion that compares at least a bit in at least a predetermined portion of a present bus signal, which is transferred between a main processing circuit and a subsidiary processing circuit at a present timing with corresponding at least a bit in at least a predetermined portion of a preceding bus signal, which is transferred between the main processing circuit and the subsidiary processing circuit at a preceding timing; and an output control portion that delays outputting, to the subsidiary processing circuit, a control signal for controlling input and output of the bus signal when the compared result shows that a predetermined difference occurs between the present bus signal and the preceding bus signal.
More specifically, the main processing circuit and the subsidiary processing circuit are connected with each other via bus. Bus signal is outputted and inputted between the main processing circuit and the subsidiary processing circuit. The bus signal may be a digital signal comprised from a plurality of bits. The input/output of the bus signal indicates either one or both of: output of the bus signal from the main processing circuit to the subsidiary processing circuit; and output of the bus signal from the subsidiary processing circuit to the main processing circuit. Representative examples of the main processing circuit include: a superordinate control circuit such as CPU and MPU; and all other circuits that output digital signals comprised from a plurality of bits. Representative examples of the subsidiary processing circuit include: memory circuits; input/output circuits; and all other circuits that receive and output digital signals comprised from a plurality of bits. The bus is constructed from at least one signal line for executing input/output of bus signals between the main processing circuit and the subsidiary processing circuit.
The signal control circuit outputs, to the subsidiary processing circuit, a control signal for controlling input/output of the bus signal. Representative examples of the control signal are: a signal for setting a timing when the subsidiary processing circuit receives a bus signal; a signal for setting a timing when the subsidiary processing circuit stores the bus signal therein; a signal for setting a timing when the subsidiary processing circuit outputs the bus signal to the main processing circuit.
The signal control circuit includes the comparing portion and the output control portion. The comparing portion is for comparing at least a bit located in at least a predetermined portion of all the bits constituting a present bus signal, that is inputted/outputted between the main processing circuit and the subsidiary processing circuit at a present timing, with at least a bit located in at least a predetermined portion of all the bits constituting a preceding bus signal, that has been inputted/outputted between the main processing circuit and the subsidiary processing circuit at a timing preceding to the present timing. Here, the xe2x80x9cat least one bit in at least the predetermined portion of all the bits constituting the bus signalxe2x80x9d indicates at least one bit constituting a part of all the bits in the bus signal or at least one bit constituting the entire part of all the bits in the bus signal.
The output control portion delays output of the control signal from the signal control circuit to the subsidiary processing circuit when the predetermined difference occurs between the preceding bus signal and the present bus signal. By thus delaying the control signal, it is possible to delay the timing when the subsidiary processing circuit receives the bus signal or the timing when the subsidiary processing circuit outputs the bus signal to the main processing circuit.
When a plurality of bits in the bus signal simultaneously change from the preceding bus signal to the present bus signal, undesirable noise possibly occurs in the bus signal. The noise occurs immediately after the preceding bus signal changes to the present bus signal. The noise vanishes after a short period of time elapses. This short period of time is shorter than a period, at which the bus signal is repeatedly inputted to or outputted from the subsidiary processing circuit. By delaying the timing when the subsidiary processing circuit receives the bus signal or the timing when the subsidiary processing circuit outputs the bus signal to the main processing circuit, the subsidiary processing circuit can perform its bus signal receiving/outputting operation after the period of time when the noise occurs in the bus signal. The subsidiary processing circuit can therefore perform its bus signal input/output operation at timings safely shifted from the period of time when the noise occurs. It is therefore possible to prevent the subsidiary processing circuit from inputting/outputting inaccurate bus signals due to noise occurring in the bus signals.
It is preferable that the output control portion may delay the output of the control signal when at least one bit, at which the at least the predetermined portion of the present bus signal is different from the at least the predetermined portion of the preceding bus signal, has a bit pattern coinciding with a predetermined reference bit pattern.
As described already, when the plurality of bits simultaneously change from the preceding bus signal to the present bus signal, noise will possibly occur in the bus signal. Such noise may possibly occur only when the bits, at which the present signal changes from the preceding bus signal, present either one of a limited number of reference bit patterns.
In this respect, it is preferable that each of the reference bit patterns be previously determined so that noise will occur when the bus signal changes from the preceding bus signal to the present bus signal in that reference bit pattern. When bits, at which the present bus signal changes from the preceding bus signal, have the reference bit pattern, the control signal, to be outputted from the signal control circuit to the subsidiary processing circuit, is delayed. The subsidiary control circuit can therefore receive/output bus signals at appropriate timings that are safely shifted from the noise occurring time period. It is noted that a single reference bit pattern may be previously determined. Or, a plurality of reference bit patterns may be previously determined.
It is preferable that the output control portion may delay the output of the control signal when the number of bits, at which the at least the predetermined portion of the present bus signal is different from the at least predetermined portion of the preceding bus signal, is greater than or equal to a predetermined reference value.
Noise will possibly occur in the bus signal when a plurality of bits simultaneously change from the preceding bus signal to the present bus signal. It is noted, however, that there is a little possibility that noise will occur if only a small number of bits, such as two or three bits, simultaneously change from the preceding bus signal to the present bus signal. Contrarily, noise highly possibly occurs in the bus signal if a large number of bits simultaneously change. That is, noise highly possibly occurs if the number of the simultaneously-changing bits is large to some degree. Considering this fact, the reference value is set previously. When the number of bits, at which the bus signal changes from the preceding bus signal to the present bus signal, is greater than or equal to the reference value, the control signal is delayed being outputted from the signal control circuit to the subsidiary processing circuit. The subsidiary processing circuit can therefore perform its bus signal receiving operation, its bus signal outputting operation at timings that are properly shifted from the period of time when noise occurs.
It is preferable that the output control portion may delay the output of the control signal when all the bits in the predetermined portion of the present bus signal are different from the corresponding all the bits in the predetermined portion of the preceding bus signal.
Noise will possibly occur in the bus signal immediately after all the bits constituting the predetermined portion of the bus signal changes from the preceding bus signal to the present bus signal. In this case, the control signal is delayed being outputted from the signal control circuit to the subsidiary processing circuit. Thus, the subsidiary control circuit can perform its bus signal receiving/outputting operation at timings safely shifted from the noise occurring time period.
It is preferable the signal control circuit may further include a reference bit pattern changing portion that changes the predetermined reference bit pattern based on a reference bit pattern setting signal inputted from outside.
It is conceivable to change the bus, to be used, after the signal control circuit is produced. It is also conceivable not to use a part of the bus after the signal control circuit is produced. Which bit pattern change in the bus signal is liable to produce noise depends on: the ground strength of the circuit substrate, on which the signal control circuit and the subsidiary processing, circuit are mounted; and how the bus is arranged on the circuit substrate. In this respect, it is preferable to set the reference bit pattern as suitable for actual use through changing the reference bit pattern according to the instruction inputted from outside.
It is preferable that the signal control circuit may further include a reference value changing portion that changes the predetermined reference value based on a reference value setting signal inputted from outside.
As described above, noise will possibly occur in the bus signal when the number of bits that change simultaneously is large to some extent. It is, however, conceivable to change the bus to be used after the signal control circuit is produced. It is also conceivable not to use a part of the bus after the signal control circuit is produced. Whether noise occurs or not depends on: the ground strength of the circuit substrate, on which the signal control circuit, the subsidiary processing circuit are mounted; and how the bus is arranged on the circuit substrate. In this respect, it is preferable to set the reference value as suitable for actual use through changing the reference value according to the instruction inputted from outside.
It is preferable that the signal control circuit may further include a delay time period changing portion that changes a period of delay time, by which the output control portion delays the output of the control signal, based on a delay time period setting signal inputted from outside.
As described above, noise will possibly occur immediately after the preceding bus signal changes into the present bus signal. The noise then vanishes after a short period of tame elapses, where the short period of time is shorter than a time period, at which the bus signals are repeatedly inputted and outputted at the subsidiary processing circuit. The period of time where the noise remains depends on: the ground strength of the circuit substrate, on which the signal control circuit, the subsidiary processing circuit are mounted; how the bus is arranged on the circuit substrate; and the operation speed of the subsidiary processing circuit. In this respect, it is preferable to set the delay time as suitable for actual use through changing, according to the instruction from outside, the amount of time that output of the control signal is to be delayed.
It is preferable that the signal control circuit may further include a comparing bit changing portion that changes, based on a bit setting signal inputted from outside, at least one bit in the preceding bus signal and at least one bit in the present bus signal as subjects to be compared by the comparing portion.
As described above, the comparator in the signal control circuit compares at least a bit in at least the predetermined portion of all the bits in the preceding bus signal with at least a bit in at least the predetermined portion of all the bits in the present bus signal. Those bits in the bus signal that should be subjected to the comparing operation should be changed according to the actual use. It is therefore preferable that a part in the bits of the preceding bus signal and a part in the bits of the present bus signal, to be subjected to the comparing operation, be changed according to the instruction inputted from outside. That is, the bit numbers of the bits or the range of the bits, in each of the preceding bus signal and the present bus signal, to be subjected to the comparing operation is changed according to the instruction inputted from outside. The bus signal comparing operation can therefore be achieved as suitable for actual use.
According to another aspect, the present invention provides a signal control circuit, provided between a main processing circuit for outputting an address signal to designate an address and a dynamic RAM that performs data reading operation and data writing operation to the address designated by the address signal outputted from the main processing circuit, and being for receiving the address signal from the main processing circuit, for dividing the address signal into row address and column address, for outputting the row address and column address in a predetermined order to the dynamic RAM while outputting, to the dynamic RAM, a control signal for controlling timings when the dynamic RAM reads the row address and the column address, the control signal circuit comprising: a comparing portion that compares, when column address, included in a present address signal outputted from the main processing circuit at a present time, is to be outputted subsequent to row address included in the present address signal, each bit at least in a predetermined portion of the column address with a corresponding bit at least in the predetermined portion of the row address, and that compares, when column address, included in the present address signal, is to be outputted subsequent to another column address included in a preceding address signal that is outputted from the main processing circuit at a preceding time, each bit at least in a predetermined portion of the column address included in the present address signal with a corresponding bit at least in the predetermined portion of the column address included in the preceding address signal; and an output control portion that delays outputting a control signal when the compared results show that a predetermined difference occurs between the addresses compared by the comparing portion.
In the above-described structure, the signal control circuit divides the address signal, outputted from the main processing circuit, into row address and column address, and outputs, to the dynamic RAM, the row address and the column address in the previously-set order. For example, the signal control circuit outputs the row address and the column address in alternation. Or, the signal control circuit may successively output column addresses after outputting a row address only once. The dynamic RAM reads the row address and the column address at timings when the dynamic RAM receives a control signal outputted from the signal controlling circuit.
When the signal control circuit outputs the column address, included in the present address signal, next to the row address included in the same present address signal, the comparing portion compares each bit at least in the predetermined portion of the column address with a corresponding bit at least in the predetermined portion of the row address. When the predetermined difference occurs between the row address and the column address, the output control portion delays outputting the control signal from the signal control circuit to the dynamic RAM.
When the signal control circuit outputs the column address, included in the present address signal, next to the column address included in the preceding address signal, the comparing portion compares each bit at least in the predetermined portion of the column address included in the present address signal with a corresponding bit at least in the predetermined portion of the column address included in the preceding address signal. When the predetermined difference occurs between the column addresses, the output control portion delays outputting the control signal from the signal control circuit to the dynamic RAM.
Thus, two successive addresses, that are successively outputted from the signal control circuit to the dynamic RAM, are compared with each other. Based on the compared results, output of the control signal is delayed. With this control, the dynamic RAM can read address signals at timings that are properly shifted from the period of time where noise occurs. It is possible to prevent the dynamic RAM from being designated with inaccurate addresses.
According to another aspect, the present invention provides a signal control system, comprising: a main processing circuit for mainly processing a bus signal; a subsidiary processing circuit capable of communicating the bus signals with the main processing circuit via a bus; and a signal control circuit, provided between the main processing circuit and the subsidiary processing circuit, the signal control circuit including: means for receiving the bus signals that are successively inputted to or outputted from the subsidiary processing circuit, and means for outputting control signals to the subsidiary processing circuit, thereby controlling at least one of input and output of the bus signals to and from the subsidiary processing circuit; and means for comparing at least a predetermined portion in all of a plurality of bits constituting a present bus signal, which is inputted to or outputted from the subsidiary processing circuit at a present timing, with at least the predetermined portion in all of a plurality of bits constituting a preceding bus signal, which is inputted to or outputted from the subsidiary processing circuit at a timing preceding to the present timing, the comparing means instructing the control signal outputting means to delay output of the control signal, for controlling a corresponding one of input and output of the present bus signal, to the subsidiary processing circuit when the compared result shows that a predetermined difference occurs between the present bus signal and the preceding bus signal.
According to still another aspect, the present invention provides a dynamic RAM control system, comprising: a main processing circuit for outputting an address signal to designate an address; a dynamic RAM that performs data reading operation and data writing operation to the address designated by the address signal outputted from the main processing circuit; and a signal control circuit, provided between the main processing circuit and the dynamic RAM, for receiving the address signal from the main processing circuit, the signal control circuit including: means for receiving address signals successively outputted from the main processing circuit, for dividing each received address signal into row address and column address, for outputting at least one of the row address and the column address in a predetermined order to the dynamic RAM, while outputting, to the dynamic RAM, a control signal for controlling a timing when the dynamic RAM reads the outputted at least one of the row address and the column address; and means for, when the output means outputs column address, included in a present address signal that is received from the main processing circuit at a present time, next to row address included also in the present address signal, comparing each bit at least in a predetermined portion of the column address with a corresponding bit at least in the predetermined portion of the row address, and for, when the output means outputs column address, included in the present address signal, next to another column address included in a preceding address signal that is outputted from the main processing circuit at a timing preceding to the present timing, comparing each bit at least in a predetermined portion of the column address included in the present address signal with a corresponding bit at least in the predetermined portion of the column address included in the preceding address signal, the comparing means outputting a delay request signal to the output means when the compared results show that a predetermined difference occurs between the addresses compared by the comparing portion, thereby controlling the output means to delay outputting the control signal for controlling a timing when the dynamic RAM is to read the column address that is included in the present address signal.